Design space exploration of network on chip:a system level approach
Jana**, Rabindra Ku
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In this paper, we have proposed a model for design space exploration of a mesh based Network on Chip architecture at system level. The main aim of the paper is, to find the topological mapping of intellectual properties (IPs) into a mesh-based Network on Chip( NoC), to minimize energy and maximum bandwidth requirement. A heuristic technique based on multi-objective genetic algorithm is proposed to obtain an optimal approximation of the pareto-optimal front. We used “manymany” mapping between switch and cores (IPs) instead of “one-one” mapping. The experiments are performed on randomly generated benchmarks and a real application (a M-JPEG encoder) is shown to illustrate the efficiency, accuracy and scalability of the proposed model.